公开(公告)号：US11101170B2

公开(公告)日：2021-08-24

申请号：US16509947

申请日：2019-07-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Motoi Ichihashi ,  Atsushi Ogino

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

公开(公告)号：US12046651B2

公开(公告)日：2024-07-23

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L23/5286

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

公开(公告)号：US20230132912A1

公开(公告)日：2023-05-04

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L29/423 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.