公开(公告)号：US20220343988A1

公开(公告)日：2022-10-27

申请号：US17860380

申请日：2022-07-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Balaji JAYARAMAN ,  Toshiaki KIRIHATA ,  Amit K. MISHRA

IPC: G11C17/18 ,  G11C29/50

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

公开(公告)号：US20230027165A1

公开(公告)日：2023-01-26

申请号：US17380688

申请日：2021-07-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramesh RAGHAVAN ,  Balaji JAYARAMAN ,  Ming YIN

IPC: G11C29/50 ,  G11C7/12 ,  G11C8/08

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.