公开(公告)号：US6165869A

公开(公告)日：2000-12-26

申请号：US96047

申请日：1998-06-11

申请人： Gang Qian ,  Chock Hing Gan ,  Lap Hung Chan ,  Poh Suan Tan

发明人： Gang Qian ,  Chock Hing Gan ,  Lap Hung Chan ,  Poh Suan Tan

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method is described for filling trenches with dielectric for shallow trench isolation which completely fills the trench and avoids problems due to dishing at the top of the trench. A trench is formed in a substrate having a second dielectric material formed thereon. The trench is lined with a third dielectric material. Sub atmospheric chemical vapor deposition, SACVD, of tetra-ethyl-ortho-silicate and ozone is used to grow a fourth dielectric on the surface of the second dielectric material and in the trench lined with the third dielectric material. The growth rate of fourth dielectric on the third dielectric is greater than the growth rate of the fourth dielectric on the second dielectric using SACVD of tetra-ethyl-ortho-silicate and ozone. The difference in growth rate assures that the trench is completely filled with fourth dielectric even for relatively thin layers of fourth dielectric grown on the second dielectric. This provides good planarity for a planarized substrate and avoids the problem of dishing at the top of the trench.

摘要翻译： 描述了一种用于填充具有用于浅沟槽隔离的电介质的沟槽的方法，其完全填充沟槽并且避免了由于沟槽顶部的凹陷引起的问题。 在其上形成有第二电介质材料的基板中形成沟槽。 沟槽衬有第三介电材料。 使用四乙基原硅酸盐和臭氧的次大气化学气相沉积，SACVD在第二介电材料的表面上和在第三介电材料内衬的沟槽中生长第四电介质。 第四电介质的第四电介质的生长速率大于使用四乙基原硅酸盐和臭氧的SACVD的第二电介质上的第四电介质的生长速率。 生长速率的差异确保即使对于在第二电介质上生长的第四电介质的较薄层，沟槽也完全填充第四电介质。 这为平坦化衬底提供了良好的平面性，并且避免了在沟槽顶部的凹陷的问题。

公开(公告)号：US06307248B1

公开(公告)日：2001-10-23

申请号：US09289890

申请日：1999-04-12

申请人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

发明人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

IPC分类号： H01L2900

CPC分类号： H01L27/11803 ,  Y10S438/922

摘要： A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

摘要翻译： 描述了在限定反熔丝窗口中使用未掺杂的多晶硅膜作为掩模来制造抗熔丝电池的方法。 在半导体衬底的表面上设置一层氧化硅。 第一未掺杂的多晶硅层沉积在氧化硅层上。 第一未掺杂的多晶硅层被图案化以形成掩模的光致抗蚀剂层覆盖。 将第一未掺杂的多晶硅层和一部分氧化硅层蚀刻掉，其中它们不被掩模覆盖以形成电池开口。 除去孔中的掩模和剩余的氧化硅。 绝缘层沉积在第一未掺杂多晶硅层的表面上并且在电池开口内。 第二多晶硅层沉积在绝缘层上并掺杂。 将第二多晶硅层图案化以形成抗熔丝电池。 形成栅电极和源极和漏极区，完成集成电路器件的制造。

公开(公告)号：US6001706A

公开(公告)日：1999-12-14

申请号：US986670

申请日：1997-12-08

申请人： Poh Suan Tan ,  Lap Chan ,  Qinghua Zhong ,  Qian Gang

发明人： Poh Suan Tan ,  Lap Chan ,  Qinghua Zhong ,  Qian Gang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas. This eliminates the wrap-around corner effect which in the prior art resulted in enhanced corner conduction and increased sub-threshold leakage currents at substrate back bias. This improved method also provides greater processing latitude during the chemical mechanical polish step.

摘要翻译： 实现了一种用于制造具有自对准并在器件区域的边缘上延伸的凸起部分的场氧化物区域（浅沟槽隔离）的方法。 这导致FET具有改进的亚阈值特性和较低的亚阈值漏电流。 该方法包括在硅衬底上形成衬垫氧化物并沉积掺杂多晶硅层和硬掩模层。 浅沟槽通过硬掩模，掺杂多晶硅层并部分地蚀刻到硅衬底中。 使用热氧化在沟槽中形成衬垫氧化物，并以更高的氧化速率氧化掺杂多晶硅层的侧壁，以在器件区域的边缘上形成氧化物。 间隙填充氧化物沉积在沟槽和化学机械抛光（CMP）中回到多晶硅层。 选择性地去除器件区域上的剩余多晶硅层以提供具有形成在器件区域的边缘上的凸起部分的场氧化物。 这消除了环绕拐角效应，其在现有技术中导致增强的拐角传导和在衬底背偏压下增加的次阈值泄漏电流。 这种改进的方法还在化学机械抛光步骤期间提供更大的加工纬度。