公开(公告)号：US06745371B2

公开(公告)日：2004-06-01

申请号：US10098756

申请日：2002-03-15

申请人： George K. Konstadinidis ,  Harry Ma ,  Alan P. Smith ,  Kevin J. Wu

发明人： George K. Konstadinidis ,  Harry Ma ,  Alan P. Smith ,  Kevin J. Wu

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： Performance of an integrated circuit design, whether embodied as a design encoding or as a fabricated integrated circuit, can be improved by selectively substituting low Vt transistors in a way that prioritizes substitution opportunities based on multi-path timing analysis and evaluates such opportunities based on one or more substitution constraints. By valuing, in a prioritization of substitution opportunities, contributions for all or substantially all timing paths through the substitution opportunity that violate a max-time constraint, repeated passes through a timing analysis phase can be advantageously avoided or limited. In addition, by recognizing one or more constraints on actual low Vt substitutions, particular noise-oriented constraints, the scope of post substitution design analysis can be greatly reduced. In some realizations, substitutions are performed so long as a leakage current budget is not expended. As a result, integrated circuit designs prepared in accordance with the described techniques may exhibit substantial cycle time improvements through judicious selection of gate instances for substitution. In some realizations, improved yields of high grade parts may result.

摘要翻译： 集成电路设计的性能，无论体现为设计编码还是作为制造集成电路，都可以通过以基于多路径时序分析优先考虑替代机会的方式选择性地替代低Vt晶体管来提高，并基于一个 或更多的替代约束。 通过估价替代机会的优先级，通过违反最大时间约束的替代机会对所有或基本上所有定时路径的贡献，可以有利地避免或限制重复通过时序分析阶段。 此外，通过识别对实际的低Vt取代的一个或多个约束，特定的面向噪声的约束，可以大大降低后置换设计分析的范围。 在一些实现中，只要泄漏电流预算不被消耗，则执行替换。 因此，根据所描述的技术制备的集成电路设计可以通过明智地选择用于替代的门实例来显示大量的周期时间改进。 在某些实现中，可能会导致高品位部件的产量提高。