公开(公告)号：US06718530B2

公开(公告)日：2004-04-06

申请号：US10207678

申请日：2002-07-29

申请人： Ghun Kim ,  Yet-Ping Pai

发明人： Ghun Kim ,  Yet-Ping Pai

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： One embodiment of the present invention provides a system that considers inductive effects while analyzing noise and propagation delay effect in a circuit layout. The system operates by first receiving the circuit layout, wherein the circuit layout specifies a plurality of nets that carry signals between circuit elements. Next, the system converts a given net into a single signal path, which is divided into a number of segments. The system then calculates inductance, capacitance, and resistance values for each segment. Next, the system uses these inductance, capacitance, and resistance values to produce a model for each segment. The system then couples together models for each segment into a model for the given net. The system uses the model for the given net to determine a noise and propagation delay effect through the given net.

摘要翻译： 本发明的一个实施例提供一种在电路布局中分析噪声和传播延迟效应的同时考虑电感效应的系统。 系统通过首先接收电路布局来操作，其中电路布局指定在电路元件之间传送信号的多个网络。 接下来，系统将给定的网络转换成单个信号路径，其被分成多个段。 然后系统计算每个段的电感，电容和电阻值。 接下来，系统使用这些电感，电容和电阻值为每个段产生一个模型。 然后，系统将每个段的模型耦合到给定网的模型中。 系统使用给定网络的模型来确定通过给定网络的噪声和传播延迟效应。

公开(公告)号：US07137091B1

公开(公告)日：2006-11-14

申请号：US10778639

申请日：2004-02-13

申请人： Dae Suk Jung ,  Manoj Gopalan ,  Yu-Yen Mo ,  Seong Rai Cho ,  Venkat R. Podduturi ,  Yet-Ping Pai

发明人： Dae Suk Jung ,  Manoj Gopalan ,  Yu-Yen Mo ,  Seong Rai Cho ,  Venkat R. Podduturi ,  Yet-Ping Pai

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of a circuit, the net being divided into two nets. One net includes internal circuit elements of a processor component and another net includes external circuit elements of a processor component. A repeater solution, which includes inserted repeaters coupled to the internal circuit elements, is instantiated to other processor components. Subsequently, after instantiation of the repeater solution, repeaters are inserted in the nets external to the processor component.

摘要翻译： 在处理器层级中用于在不同级别插入中继器的方法和系统涉及在处理器电路中跟踪网络，然后在网络中的不同位置插入中继器。 网络是电路的电路元件之间的布线的电路图，网被分成两个网。 一个网络包括处理器组件的内部电路元件，另一个网络包括处理器组件的外部电路元件。 包括连接到内部电路元件的插入式中继器的中继器解决方案被实例化到其他处理器组件。 随后，在中继器解决方案实例化之后，将中继器插入到处理器组件外部的网络中。

公开(公告)号：US06738959B2

公开(公告)日：2004-05-18

申请号：US10211632

申请日：2002-08-02

申请人： Dae Suk Jung ,  Seong Rai Cho ,  Yet-Ping Pai

发明人： Dae Suk Jung ,  Seong Rai Cho ,  Yet-Ping Pai

IPC分类号： G06F1750

CPC分类号： G06F17/5077

摘要： One embodiment of the present invention provides a system that facilitates routing nets between cells in a circuit layout. During operation, the system receives a circuit design to be routed, wherein the circuit design includes multiple circuit blocks that have been placed at specific locations within the circuit layout. Next, the system determines estimated lengths for nets that couple these circuit blocks together. The system then calculates the delay for the nets that couple the circuit blocks using a class one rule. If the delay in a given net is greater than a specified delay, the system inserts a virtual repeater into the given net to decrease the delay.

公开(公告)号：US6110221A

公开(公告)日：2000-08-29

申请号：US879660

申请日：1997-06-23

申请人： Yet-Ping Pai ,  Khanh Le ,  Kong-Fai Woo

发明人： Yet-Ping Pai ,  Khanh Le ,  Kong-Fai Woo

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L25/00 ,  H03K19/0175 ,  H03K19/177

CPC分类号： G06F17/5068 ,  H01L27/0207

摘要： The present invention organizes the circuits on a VLSI chip into clusters. A number of channels exist in-between the clusters. Blocks of repeaters are used in a linear array, and are placed adjacent the edges of the clusters where repeaters are estimated to be needed. The repeater cells themselves are preferably formed to have a width less than or equal to the width of a line track for routing lines such that an array of repeater cells can be lined up with an array of routing lines in a bus.

摘要翻译： 本发明将VLSI芯片上的电路组织成簇。 集群之间存在多个通道。 中继器块以线性阵列使用，并且被放置在与需要中继器的簇的边缘相邻处。 中继器单元本身优选地形成为具有小于或等于用于布线的线路的宽度的宽度，使得中继器单元的阵列可以与总线中的布线线阵列对齐。

公开(公告)号：US5860158A

公开(公告)日：1999-01-12

申请号：US751149

申请日：1996-11-15

申请人： Yet-Ping Pai ,  Le T. Nguyen

发明人： Yet-Ping Pai ,  Le T. Nguyen

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/084

摘要： A cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the requesting device. The first cache request may begin to be processed. A second cache request is received from the cache accessing device. The second cache request is assigned to the first cache request and provided to the requesting device. The first and second cache requests are finally fully serviced.

摘要翻译： 高速缓存控制单元和控制高速缓存的方法。 缓存耦合到高速缓存访​​问设备。 从设备接收到第一个缓存请求。 请求识别信息被分配给第一高速缓存请求并提供给请求设备。 第一个缓存请求可能开始被处理。 从高速缓存访​​问设备接收第二高速缓存请求。 第二缓存请求被分配给第一高速缓存请求并提供给请求设备。 第一个和第二个缓存请求终于被完全服务了。