公开(公告)号：US07774399B2

公开(公告)日：2010-08-10

申请号：US12148515

申请日：2008-04-18

申请人： Gibson Dana Elliot ,  Charles H. Moore

发明人： Gibson Dana Elliot ,  Charles H. Moore

IPC分类号： G06F7/52

CPC分类号： G06F7/582

摘要： A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.

摘要翻译： 一种用于对多个因素执行并行乘法的系统。 在二进制处理器中，第一和第二存储器具有多个位位置。 第一存储器保持第一值作为通常用作因子的倍数的乘数，并且第二存储器保存代表作为其他因素的多个被乘数的第二值。 确定乘法器中有效位的乘法器位计数。 并且使用第一值和所述第二值执行+ *操作等于乘数位计数的次数。

公开(公告)号：US20090083360A1

公开(公告)日：2009-03-26

申请号：US12148515

申请日：2008-04-18

申请人： Gibson Dana Elliot ,  Charles H. Moore

发明人： Gibson Dana Elliot ,  Charles H. Moore

IPC分类号： G06F7/523

CPC分类号： G06F7/582

摘要： A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.

摘要翻译： 一种用于对多个因素执行并行乘法的系统。 在二进制处理器中，第一和第二存储器具有多个位位置。 第一存储器保持第一值作为通常用作因子的倍数的乘数，并且第二存储器保存代表作为其他因素的多个被乘数的第二值。 确定乘法器中有效位的乘法器位计数。 并且使用第一值和所述第二值执行+ *操作等于乘数位计数的次数。