公开(公告)号：US20130173977A1

公开(公告)日：2013-07-04

申请号：US13342030

申请日：2011-12-31

申请人： Girishankar Gurumurthy ,  Mehesh Ramdas Vasishta

发明人： Girishankar Gurumurthy ,  Mehesh Ramdas Vasishta

IPC分类号： G01R31/3177 ,  H03K3/289

CPC分类号： H03K3/35625 ,  G01R31/318552

摘要： A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.

摘要翻译： 主/从锁存器包括输入级，主锁存器，从锁存器，以及接收异步清零信号。 输入级被布置为响应于时钟信号和门控时钟信号交替地传递或阻塞数据输入信号。 门控时钟信号是当异步清除信号未被置位时的时钟信号的倒数，当异步清除信号被置位时门控时钟信号不活动。 主锁存器以锁存状态接收并锁存通过的数据信号，响应于异步清零信号被断言而清除锁存状态，并产生主锁存输出信号。 从锁存器在锁存状态下接收并锁存主锁存器输出信号。 响应于异步清除信号被断言，清除的锁存状态被传递到从锁存器。