UART automatic half-duplex direction control with programmable delay
    1.
    发明授权
    UART automatic half-duplex direction control with programmable delay 有权
    UART自动半双工方向控制,具有可编程延迟

    公开(公告)号:US06865626B1

    公开(公告)日:2005-03-08

    申请号:US09527634

    申请日:2000-03-17

    IPC分类号: H04L7/00 G06F13/38 G06F3/00

    CPC分类号: G06F13/385

    摘要: A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART.

    摘要翻译: 提供具有FIFO缓冲器的UART。 电路检测从FIFO缓冲器发送的最后一个字。 当检测到从FIFO缓冲器发送的最后一个字时,发送器空电路产生发送器空信号(RTS)。 延迟电路延迟RTS信号的产生,用于可编程时间延迟。 经由可由用户编程的寄存器的时间延迟。 因此,本发明在与UART相同的芯片上提供可编程延迟。

    UART with compressed user accessible interrupt codes
    2.
    发明授权
    UART with compressed user accessible interrupt codes 有权
    UART具有压缩用户可访问的中断代码

    公开(公告)号:US06947999B1

    公开(公告)日:2005-09-20

    申请号:US09528089

    申请日:2000-03-17

    IPC分类号: H04B7/26 G06F13/38 G06F15/16

    CPC分类号: G06F13/385

    摘要: An improved UART which has a number of channels, with each channel having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate the source of the interrupt. This code is chosen to be compatible with prior UART devices. The device also includes a bus interface, and a plurality of device configuration registers accessible through the bus interface by a user. One of the device configuration registers is an interrupt register which provides a user accessible code to indicate the interrupt source. The code used for the interrupt source is a compressed version of the multiple bit code used in the channel configuration interrupt source register. This compression allows more channels to be represented in a single register, while also conveying the interrupt source information quickly to the user. Since the device interrupt register in the configuration registers is for access by the user, rather than internal access by UART drivers, there is no need for compatibility with the prior UART drivers.

    摘要翻译: 具有多个通道的改进的UART,每个通道具有一组通道配置寄存器。 每个通道配置寄存器包括一个中断源寄存器。 中断源寄存器有一个多位中断源代码,用于指示中断源。 该代码被选择为与以前的UART器件兼容。 该设备还包括总线接口以及用户可通过总线接口访问的多个设备配置寄存器。 设备配置寄存器之一是一个中断寄存器,提供用户可访问的代码来指示中断源。 用于中断源的代码是通道配置中断源寄存器中使用的多位代码的压缩版本。 该压缩允许在单个寄存器中表示更多的通道,同时还向用户快速传递中断源信息。 由于配置寄存器中的器件中断寄存器是用户访问的,而不是UART驱动程序的内部访问,因此不需要与以前的UART驱动程序兼容。