公开(公告)号：US12136649B2

公开(公告)日：2024-11-05

申请号：US17723665

申请日：2022-04-19

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Jianbo Zhou ,  Shiang Yang Ong ,  Namchil Mun ,  Hung Chang Liao ,  Zhongxiu Yang

IPC: H01L29/00 ,  H01L21/762 ,  H01L29/06

Abstract: Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.

公开(公告)号：US20230335583A1

公开(公告)日：2023-10-19

申请号：US17723665

申请日：2022-04-19

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Jianbo Zhou ,  Shiang Yang Ong ,  Namchil Mun ,  Hung Chang Liao ,  Zhongxiu Yang

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/762

Abstract: Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.