公开(公告)号：US20220129269A1

公开(公告)日：2022-04-28

申请号：US17080282

申请日：2020-10-26

Applicant: Google LLC

Inventor： Junwhan Ahn ,  Jichuan Chang ,  Andrew McCormick ,  Yuanwei Fang ,  Yixin Luo

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/03

Abstract: A method and system for processing a bit-packed array using one or more processors, including determining a data element size of the bit-packed array, determining a lane configuration of a single-instruction multiple-data (SIMD) unit for processing the bit-packed array based at least in part on the determined data element size, the lane configuration being determined from among a plurality of candidate lane configurations, each candidate lane configuration having a different number of vector register lanes and a corresponding bit capacity per vector register lane, configuring the SIMD unit according to the determined lane configuration, and loading one or more data elements into each vector register lane of the SIMD unit. SIMD instructions may be executed on the loaded one or more data elements of each vector register lane in parallel, and a result of the SIMD instruction may be stored in memory.

公开(公告)号：US11442729B2

公开(公告)日：2022-09-13

申请号：US17080282

申请日：2020-10-26

Applicant: Google LLC

Inventor： Junwhan Ahn ,  Jichuan Chang ,  Andrew McCormick ,  Yuanwei Fang ,  Yixin Luo

IPC: G06F9/30 ,  G06F1/03 ,  G06F9/38

Abstract: A method and system for processing a bit-packed array using one or more processors, including determining a data element size of the bit-packed array, determining a lane configuration of a single-instruction multiple-data (SIMD) unit for processing the bit-packed array based at least in part on the determined data element size, the lane configuration being determined from among a plurality of candidate lane configurations, each candidate lane configuration having a different number of vector register lanes and a corresponding bit capacity per vector register lane, configuring the SIMD unit according to the determined lane configuration, and loading one or more data elements into each vector register lane of the SIMD unit. SIMD instructions may be executed on the loaded one or more data elements of each vector register lane in parallel, and a result of the SIMD instruction may be stored in memory.