公开(公告)号：US11314674B2

公开(公告)日：2022-04-26

申请号：US16838796

申请日：2020-04-02

Applicant: Google LLC

Inventor： Mark William Gottscho ,  Matthew William Ashcraft ,  Thomas Norrie ,  Oliver Edward Bowen

IPC: G06F13/28 ,  G06F1/04

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.

公开(公告)号：US20240070098A1

公开(公告)日：2024-02-29

申请号：US18229616

申请日：2023-08-02

Applicant: Google LLC

Inventor： Mark William Gottscho ,  Matthew William Ashcraft ,  Thomas Norrie ,  Oliver Edward Bowen

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F1/04

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.

公开(公告)号：US11762793B2

公开(公告)日：2023-09-19

申请号：US17728478

申请日：2022-04-25

Applicant: Google LLC

Inventor： Mark William Gottscho ,  Matthew William Ashcraft ,  Thomas Norrie ,  Oliver Edward Bowen

IPC: G06F13/28 ,  G06F1/04

CPC classification number: G06F13/28 ,  G06F1/04

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.

公开(公告)号：US20220327075A1

公开(公告)日：2022-10-13

申请号：US17728478

申请日：2022-04-25

Applicant: Google LLC

Inventor： Mark William Gottscho ,  Matthew William Ashcraft ,  Thomas Norrie ,  Oliver Edward Bowen

IPC: G06F13/28

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.

公开(公告)号：US20210255976A1

公开(公告)日：2021-08-19

申请号：US16838796

申请日：2020-04-02

Applicant: Google LLC

Inventor： Mark William Gottscho ,  Matthew William Ashcraft ,  Thomas Norrie ,  Oliver Edward Bowen

IPC: G06F13/28

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.