公开(公告)号：US11829321B2

公开(公告)日：2023-11-28

申请号：US17703479

申请日：2022-03-24

Applicant: Google LLC

Inventor： Reginald Clifford Young ,  Trevor Gale ,  Sushma Honnavara-Prasad ,  Paolo Mantovani

IPC: G06F15/80

CPC classification number: G06F15/8046 ,  G06F15/8069 ,  G06F15/8084

Abstract: A systolic array cell is described, the cell including two general-purpose arithmetic logic units (ALUs) and register-file. A plurality of the cells may be configured in a matrix or array, such that the output of the first ALU in a first cell is provided to a second cell to the right of the first cell, and the output of the second ALU in the first cell is provided to a third cell below the first cell. The two ALUs in each cell of the array allow for processing of a different instruction in each cycle.

公开(公告)号：US20230325347A1

公开(公告)日：2023-10-12

申请号：US17703479

申请日：2022-03-24

Applicant: Google LLC

Inventor： Reginald Clifford Young ,  Trevor Gale ,  Sushma Honnavara-Prasad ,  Paolo Mantovani

IPC: G06F15/80

CPC classification number: G06F15/8046 ,  G06F15/8069 ,  G06F15/8084

Abstract: A systolic array cell is described, the cell including two general-purpose arithmetic logic units (ALUs) and register-file. A plurality of the cells may be configured in a matrix or array, such that the output of the first ALU in a first cell is provided to a second cell to the right of the first cell, and the output of the second ALU in the first cell is provided to a third cell below the first cell. The two ALUs in each cell of the array allow for processing of a different instruction in each cycle.

公开(公告)号：US12287756B2

公开(公告)日：2025-04-29

申请号：US18376494

申请日：2023-10-04

Applicant: Google LLC

Inventor： Reginald Clifford Young ,  Trevor Gale ,  Sushma Honnavara-Prasad ,  Paolo Mantovani

IPC: G06F15/80

Abstract: A systolic array cell is described, the cell including two general-purpose arithmetic logic units (ALUs) and register-file. A plurality of the cells may be configured in a matrix or array, such that the output of the first ALU in a first cell is provided to a second cell to the right of the first cell, and the output of the second ALU in the first cell is provided to a third cell below the first cell. The two ALUs in each cell of the array allow for processing of a different instruction in each cycle.

公开(公告)号：US20240078212A1

公开(公告)日：2024-03-07

申请号：US18376494

申请日：2023-10-04

Applicant: Google LLC

Inventor： Reginald Clifford Young ,  Trevor Gale ,  Sushma Honnavara-Prasad ,  Paolo Mantovani

IPC: G06F15/80

CPC classification number: G06F15/8046 ,  G06F15/8069 ,  G06F15/8084

Abstract: A systolic array cell is described, the cell including two general-purpose arithmetic logic units (ALUs) and register-file. A plurality of the cells may be configured in a matrix or array, such that the output of the first ALU in a first cell is provided to a second cell to the right of the first cell, and the output of the second ALU in the first cell is provided to a third cell below the first cell. The two ALUs in each cell of the array allow for processing of a different instruction in each cycle.