公开(公告)号：US5586253A

公开(公告)日：1996-12-17

申请号：US356561

申请日：1994-12-15

申请人： Gregory M. Green ,  Steven Kohalmi ,  Karen R. Bricknell

发明人： Gregory M. Green ,  Steven Kohalmi ,  Karen R. Bricknell

IPC分类号： G06F11/14 ,  G06F11/00

CPC分类号： G06F11/141

摘要： A novel mapping and protection circuit arrangement comprises a plurality of checking mechanisms that collectively cooperate to verify the accuracy of I/O addresses generated by input/output (I/O) controllers of a fault-tolerant computer. These verified I/O addresses are translated into system addresses to enable direct memory access (DMA) transactions between the controllers and the computer's host memory. Specifically, certain of the checking mechanisms cooperate to ensure that the DMA accesses are directed to correct pages in host memory, while other checking mechanisms are provided to ensure that memory access operations are performed at correct locations within the page. Additional checking mechanisms are provided to further verify the accuracy of generated I/O addresses.

摘要翻译： 一种新颖的映射和保护电路装置包括多个检查机制，其共同协作以验证由容错计算机的输入/输出（I / O）控制器产生的I / O地址的精度。 这些验证的I / O地址被转换为系统地址，以便在控制器和计算机的主机存储器之间实现直接内存访问（DMA）事务。 具体来说，某些检查机制协作以确保DMA访问被引导到主机存储器中的正确页面，而提供其他检查机制以确保在页面内的正确位置执行存储器访问操作。 提供额外的检查机制，以进一步验证生成的I / O地址的准确性。