公开(公告)号：US20070090452A1

公开(公告)日：2007-04-26

申请号：US11299544

申请日：2005-12-12

申请人： Gyu Seog Cho ,  Yong Taik Kim

发明人： Gyu Seog Cho ,  Yong Taik Kim

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66621

摘要： The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

摘要翻译： 所述凹槽通道晶体管包括：半导体衬底，其包括限定形成有凹部的激活区域的器件绝缘层; 绝缘缓冲图案，其各自形成在基板的表面上的凹部的开口处; 栅极，每个栅极包括形成在凹部中的凹槽和形成在衬底上的顶栅; 间隔件，每个间隔件形成在门的两侧; 以及源极区和漏极区，形成在衬底表面上的每个栅极的两侧，其中由于存在绝缘缓冲图案，源区和漏区具有均匀的掺杂分布。 因此，可以防止晶体管的特性由于顶栅与凹槽的不对准而劣化。

公开(公告)号：US07482230B2

公开(公告)日：2009-01-27

申请号：US12020686

申请日：2008-01-28

申请人： Gyu Seog Cho ,  Yong Taik Kim

发明人： Gyu Seog Cho ,  Yong Taik Kim

IPC分类号： H01L21/335

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66621

摘要： The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

摘要翻译： 所述凹槽通道晶体管包括：半导体衬底，其包括限定形成有凹部的激活区域的器件绝缘层; 绝缘缓冲图案，其各自形成在基板的表面上的凹部的开口处; 栅极，每个栅极包括形成在凹部中的凹槽和形成在衬底上的顶栅; 间隔件，每个间隔件形成在门的两侧; 以及源极区和漏极区，形成在衬底表面上的每个栅极的两侧，其中由于存在绝缘缓冲图案，源区和漏区具有均匀的掺杂分布。 因此，可以防止晶体管的特性由于顶栅与凹槽的不对准而劣化。

公开(公告)号：US08237215B2

公开(公告)日：2012-08-07

申请号：US12346959

申请日：2008-12-31

申请人： Yong Taik Kim ,  Tae Su Jang

发明人： Yong Taik Kim ,  Tae Su Jang

IPC分类号： H01L29/78

CPC分类号： H01L21/26533 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612

摘要： An SOI device includes an SOI substrate having a structure in which a first buried oxide layer and a silicon layer are stacked in turn over a semiconductor substrate. A gate is formed over the silicon layer of the SOI substrate. A second buried oxide layer is formed at both sides of the gate in a lower portion of the silicon layer so that a lower end portion of the second buried oxide layer is in contact with the first buried oxide layer. A junction region is then formed in the portion of the silicon layer above the second buried oxide layer so that the lower end portion of the junction region is in contact with the second buried oxide layer.

摘要翻译： SOI器件包括具有其中第一掩埋氧化物层和硅层依次堆叠在半导体衬底上的结构的SOI衬底。 在SOI衬底的硅层上形成栅极。 第二掩埋氧化物层在硅层的下部形成在栅极的两侧，使得第二掩埋氧化物层的下端部与第一掩埋氧化物层接触。 然后在第二掩埋氧化物层上方的硅层的部分中形成结区，使得接合区的下端部与第二掩埋氧化物层接触。