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公开(公告)号：US11520965B2
公开(公告)日：2022-12-06
申请号：US16769164
申请日：2018-01-08
发明人： Chengli Liu , Haili Wang , Zixian Chen , Ming Ma
IPC分类号： G06F30/30 , G06F30/347
摘要： A programmable device includes a functional module, a pre-allocation manager, a first connection line, and a second connection line, wherein the pre-allocation managers are connected by the first connection lines, and the pre-allocation managers are connected to the functional modules by the second connection lines; the first connection lines are used for data transmission between the pre-allocation mangers, and a transmission direction is determined according to the configuration; the second connection lines are used for data transmission between the pre-allocation managers and the functional modules; the pre-allocation mangers are used for data transmission between the first connection lines and for data transmission between the first connection lines and the functional modules. The first connection lines are configured as connection line segments for transmission in both directions, and a wiring structure is designed in a direction and shape meeting wiring requirements.
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公开(公告)号：US11323121B2
公开(公告)日：2022-05-03
申请号：US16769152
申请日：2018-01-08
发明人： Chengli Liu , Haili Wang , Zixian Chen , Ming Ma
IPC分类号： H03K19/17 , H03K19/1776 , G06F30/34 , G11C11/418
摘要： A programmable device structure based on a mixed function storage unit includes a storage unit SRAM and a mixed function unit, wherein the storage unit comprises n register units and at least one selection control bit, wherein n=2{circumflex over ( )}x, and x is natural number; the register units are selected according to the selection control bit; and when the selection control bit selects the mixed function unit to serve as a lookup table, a logic function is achieved; or when the selection control bit selects the mixed function unit to serve as a multiplexer, a routing function is achieved. By multiplexing the register units, the programmable device structure achieves a routing function of a traditional FPGA and also provides a logic function, and the waste of resources is greatly reduced.
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公开(公告)号：US11211933B2
公开(公告)日：2021-12-28
申请号：US16769061
申请日：2018-01-08
发明人： Chengli Liu , Haili Wang , Zixian Chen , Ming Ma
IPC分类号： H03K19/17736 , H03K19/17796
摘要： An FPGA chip includes one functional unit, one pre-allocation manager, and wiring segments. The functional unit includes a first module CPE and a second module PLF. The pre-allocation manager may be connected by means of one of the wiring segments. By configuring one pre-allocation manager, data transmission directions of the wiring segments may be changed. The functional unit is connected to one pre-allocation manager by means of a conventional line. The first module CPE and the second module PLF which are adjacent in the same functional unit are connected by means of a cross-connection line. The second functional modules are interconnected by means of a conventional routing system. Different functional blocks can be connected to each other from any position of a circuit.
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