公开(公告)号：US10062137B2

公开(公告)日：2018-08-28

申请号：US15121217

申请日：2014-02-27

申请人： Hewlett Packard Enterprise Development LP

发明人： Indrajit Roy ,  Sangman Kim ,  Vanish Talwar

IPC分类号： G06T1/20 ,  G06F15/167 ,  G06F9/50 ,  G06F12/04 ,  G06F12/1009 ,  G06F12/1036 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06F9/50 ,  G06F12/04 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1072 ,  G06F15/167 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/60

摘要： The communication between integrated graphics processing units (GPUs) is disclosed. A first integrated GPU of a first computing device obtains a tuple pertaining to data to be transmitted to a second integrated GPU of a second computing device. The tuple comprises at least a length of the data. The first integrated GPU allocates a virtual address space to the data based on the length of the data, where the virtual address space has a plurality of virtual addresses. Further, a mapping table of a mapping between the plurality of virtual addresses and a plurality of bus addresses is provided by the first integrated GPU to a communication module of the first computing device to transmit the data, where the plurality of bus addresses indicate physical locations of the data.

公开(公告)号：US20170018050A1

公开(公告)日：2017-01-19

申请号：US15121217

申请日：2014-02-27

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Indrajit Roy ,  Sangman Kim ,  Vanish Talwar

IPC分类号： G06T1/20 ,  G06F15/167 ,  G06T1/60 ,  G06F12/1009 ,  G06F12/1036 ,  G06F9/50 ,  G06F12/04

CPC分类号： G06T1/20 ,  G06F9/50 ,  G06F12/04 ,  G06F12/1009 ,  G06F12/1036 ,  G06F15/167 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/60

摘要： The communication between integrated graphics processing units (CPUs) is disclosed. A first integrated GPU of a first computing device obtains a tuple pertaining to data to be transmitted to a second integrated CPU of a second computing device. The tuple comprises at least a length of the data. The first integrated GPU allocates a virtual address space to the data based on the length of the data, where the virtual address space has a plurality of virtual addresses. Further, a mapping table of a mapping between the plurality of virtual addresses and a plurality of bus addresses is provided by the first integrated GPU to a communication module of the first computing device to transmit the data, where the plurality of bus addresses indicate physical locations of the data.

摘要翻译： 公开了集成图形处理单元（CPU）之间的通信。 第一计算设备的第一集成GPU获得与要发送到第二计算设备的第二集成CPU的数据相关的元组。 元组至少包括一段长度的数据。 第一集成GPU基于数据的长度为数据分配虚拟地址空间，其中虚拟地址空间具有多个虚拟地址。 此外，由第一集成GPU向第一计算设备的通信模块提供多个虚拟地址和多个总线地址之间的映射的映射表，以发送数据，其中多个总线地址指示物理位置 的数据。