COMPILER FOR IMPLMENTING NEURAL NETWORK ACCELERATOR

    公开(公告)号:US20220121959A1

    公开(公告)日:2022-04-21

    申请号:US17229497

    申请日:2021-04-13

    IPC分类号: G06N3/10 G06N3/063

    摘要: Examples disclosed herein relate to using a compiler for implementing tensor operations in a neural network base computing system. A compiler defines the tensor operations to be implemented. The compiler identifies a binary tensor operation receiving input operands from a first output tensor of a first tensor operation and a second output tensor of a second tensor operation from two different paths of the convolution neural network. For the binary tensor operation, the compiler allocates a buffer space for a first input operand in the binary tensor operation based on a difference between a count of instances of the first output tensor and a count of instances of the second output tensor.

    EXECUTION OF NEURAL NETWORKS
    6.
    发明申请

    公开(公告)号:US20220198249A1

    公开(公告)日:2022-06-23

    申请号:US17231153

    申请日:2021-04-15

    IPC分类号: G06N3/063 G06N3/10

    摘要: Example techniques for causing execution of neural networks are described. A neural network includes a first part and a second part. A determination is made that a first physical resource in a first computing device is to execute the first part and that a second physical resource in a second computing device is to execute the second part. The determination is based on a latency in communication between the first physical resource and the second physical resource. The first computing device and the second computing device are part of a cluster.