公开(公告)号：US20140122807A1

公开(公告)日：2014-05-01

申请号：US13665490

申请日：2012-10-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, LP.

Inventor： Jichuan Chang ,  Doe Hyun Yoon ,  Parthasarathy Ranganathan

IPC: G06F12/08

CPC classification number: G06F12/1009

Abstract: Memory address translations are disclosed. An example memory controller includes an address translator to translate an intermediate memory address into a hardware memory address based on a function, the address translator to select the function based on at least a portion of the intermediate memory address, the intermediate memory address being identified by a processor. The example memory controller includes a cache to store the function in association with an address range of the intermediate memory sector, the intermediate memory address being within the intermediate memory sector. Further, the example memory controller includes a memory accesser to access a memory module at the hardware memory address.

Abstract translation: 公开了存储器地址转换。 示例性存储器控制器包括地址转换器，其基于功能将中间存储器地址转换为硬件存储器地址，地址转换器基于中间存储器地址的至少一部分来选择功能，中间存储器地址由 一个处理器 示例性存储器控制器包括高速缓存，用于存储与中间存储器扇区的地址范围相关联的功能，中间存储器地址在中间存储器扇区内。 此外，示例性存储器控制器包括存储器访问器，以在硬件存储器地址处访问存储器模块。