公开(公告)号：US20230409518A1

公开(公告)日：2023-12-21

申请号：US18036029

申请日：2021-08-31

Applicant: HITACHI ASTEMO, LTD.

Inventor： Yasuhiro IKEDA ,  Tadanobu TOBA ,  Kenichi SHIMBO ,  Atsushi ARATA ,  Takeo YAMASHITA ,  Atsushi ICHIGE ,  Shinichi NONAKA

IPC: G06F15/78 ,  G01R31/3185 ,  G06F15/177

CPC classification number: G06F15/7892 ,  G01R31/318516 ,  G06F15/177

Abstract: An arithmetic operation device executes a test using a partially reconfigurable programmable logic unit, the programmable logic unit includes a test target circuit which is a user circuit, and a non-test circuit which is a user circuit which is not the test target circuit, and the arithmetic operation device includes a configuration control unit which causes the programmable logic unit to form, by partial reconfiguration, a test partition unit which separates the test target circuit and the non-test circuit, and a partition control unit which controls the test partition unit to test the test target circuit.