ETHERNET DATA PROCESSING METHOD, PHYSICAL LAYER CHIP AND ETHERNET EQUIPMENT
    1.
    发明申请
    ETHERNET DATA PROCESSING METHOD, PHYSICAL LAYER CHIP AND ETHERNET EQUIPMENT 有权
    以太网数据处理方法,物理层芯片和以太网设备

    公开(公告)号:US20160094311A1

    公开(公告)日:2016-03-31

    申请号:US14891778

    申请日:2013-01-04

    Inventor: Wei SU Li ZENG Kai CUI

    Abstract: Embodiments of the present invention disclose an Ethernet data processing method, an Ethernet physical layer chip, and Ethernet equipment. Applicable to data processing at a transmit end, the method includes: performing line coding on data from a media access control layer, so as to obtain serial data code blocks; performing forward error correction FEC coding on the serial data code blocks, so as to obtain FEC frames, which specifically includes: inserting Y check bits every X consecutive data bits, where the Y check bits are generated when FEC coding is performed on the X consecutive data bits; and distributing, at a distribution granularity of a bits, the FEC frames successively to N virtual channels, where a and N are both positive integers, and a is less than a quantity of bits included in one FEC frame.

    Abstract translation: 本发明的实施例公开了以太网数据处理方法,以太网物理层芯片和以太网设备。 适用于发送端的数据处理,该方法包括:对来自媒体接入控制层的数据进行线路编码,以获得串行数据码块; 对串行数据代码块执行前向纠错FEC编码,以获得FEC帧,具体包括:每X个连续数据位插入Y个校验位,其中在对X连续执行FEC编码时生成Y个校验位 数据位; 并且以FEC的分布粒度分配FEC帧连续到N个虚拟信道,其中a和N都是正整数,并且a小于一个FEC帧中包括的比特量。

Patent Agency Ranking