公开(公告)号：US20190097642A1

公开(公告)日：2019-03-28

申请号：US16204790

申请日：2018-11-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hua LI ,  Yan GAO ,  Sheng MA

IPC: H03L7/099

Abstract: A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source superimposes a first direct current voltage on a first clock signal output by a first oscillation circuit, to generate a second clock signal; and a logical operation is performed on the second clock signal and a third clock signal that is generated by a second clock source, to generate a fourth clock signal. The fourth clock signal is used as a signal output by a clock generation circuit. In the method, when the first oscillation circuit cannot normally work, the clock generation circuit can still output a correct clock signal. This avoids clock signal interruption when switching is performed from the first clock source to the second clock source.