公开(公告)号：US20220091850A1

公开(公告)日：2022-03-24

申请号：US17543096

申请日：2021-12-06

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Da Qi Ren ,  Qian Wang ,  XingYu Jiang

IPC: G06F9/38 ,  G06N3/08

Abstract: The disclosure relates to branch prediction techniques that can improve the performance of pipelined microprocessors. A microprocessor for branch predictor selection includes a fetch stage configured to retrieve instructions from a memory. A buffer is configured to store instructions retrieved by the fetch stage, and one or more pipelined stages configured to execute the instructions stored in the buffer. The branch predictor, communicatively coupled to the buffer and the one or more pipelined stages, is configured to select a branch target predictor from a set of branch target predictors. Each of the branch target predictors comprise a trained model associated with a previously executed instruction to identify a target branch path for the instruction currently being executed based on the selected branch target predictor.