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公开(公告)号:US12174254B2
公开(公告)日:2024-12-24
申请号:US18308405
申请日:2023-04-27
Applicant: Huawei Technologies Co., Ltd.
Inventor: Zhe Tao , Ge Shen , Jianlong Cao , Ming Wang , Rui Fang
IPC: G01R31/3185 , G06F9/48
Abstract: A fault detection method includes: obtaining a scheduling table of a target task, where the scheduling table is used to indicate at least one test pattern, the at least one test pattern is used to detect a fault in a target logic circuit, and the target logic circuit is a logic circuit configured to execute the target task; and executing the at least one test pattern based on the scheduling table, to detect the fault in the target logic circuit.
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公开(公告)号:US11308386B2
公开(公告)日:2022-04-19
申请号:US16423750
申请日:2019-05-28
Applicant: Huawei Technologies Co., Ltd.
Abstract: A signal processing method and apparatus includes determining a first signal F1(t) output by a first neuron, processing the first signal F1(t) using q orders of synapse weight parameters wq(t), wq−1(t), . . . , w1(t) to obtain a second signal F2(t), and inputting the second signal F2(t) to a second neuron, where the second neuron is in a layer immediately subsequent to that of the first neuron.
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公开(公告)号:US20190286969A1
公开(公告)日:2019-09-19
申请号:US16423750
申请日:2019-05-28
Applicant: Huawei Technologies Co., Ltd.
Abstract: A signal processing method and apparatus includes determining a first signal F1(t) output by a first neuron, processing the first signal F1(t) using q orders of synapse weight parameters wq(t), wq−1(t), . . . , w1 (t) to obtain a second signal F2(t), and inputting the second signal F2(t) to a second neuron, where the second neuron is a next-layer neuron of the first neuron.
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公开(公告)号:US20230258718A1
公开(公告)日:2023-08-17
申请号:US18308405
申请日:2023-04-27
Applicant: Huawei Technologies Co., Ltd.
Inventor: Zhe Tao , Ge Shen , Jianlong Cao , Ming Wang , Rui Fang
IPC: G01R31/3185 , G06F9/48
CPC classification number: G01R31/318544 , G06F9/4881
Abstract: Embodiments of this application disclose a fault detection method, and relate to the field of computer technologies. The method according to embodiments of this application includes: obtaining a scheduling table of a target task, where the scheduling table is used to indicate at least one test pattern, the at least one test pattern is used to detect a fault in a target logic circuit, and the target logic circuit is a logic circuit configured to execute the target task; and executing the at least one test pattern based on the scheduling table, to detect the fault in the target logic circuit. By determining the scheduling table of the target task, the test pattern included in the scheduling table is executed, so that execution of all test patterns in a software test library can be avoided. This reduces load of a processor, and effectively improves working efficiency of the processor.
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公开(公告)号:US20220083367A1
公开(公告)日:2022-03-17
申请号:US17534462
申请日:2021-11-24
Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
Inventor: Gang Yao , Ping Chen , Ming Wang , Gang Wu , Zhiqiang Luo
Abstract: A graphics processing method and apparatus, and relates to the field of chip technologies. The method includes: obtaining a first virtual address to be accessed by the GPU, where the first virtual address belongs to a first virtual address space; and obtaining a second virtual address based on the first virtual address, where the second virtual address belongs to a second virtual address space. The second virtual address space is different from the first virtual address space, the second virtual address space and the first virtual address space are mapped to a same physical address space, a physical address to which the first virtual address is mapped corresponds to image data in a first format, and a physical address to which the second virtual address is mapped corresponds to image data in a second format.
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