公开(公告)号：US09965386B2

公开(公告)日：2018-05-08

申请号：US15233601

申请日：2016-08-10

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Hongshi Sang ,  Yinghua Gao ,  Peng Hu

IPC: G06F17/14 ,  G06F12/06

CPC classification number: G06F12/06 ,  G06F12/0207 ,  G06F17/142 ,  G06F2212/1016

Abstract: The invention discloses a method for generating a row transposed architecture based on a two-dimensional FFT processor, comprising the following characteristic: the FFT processor includes an on-chip row transposition memory for storing an image row transposition result. When the size of the row transposition result exceeds the capacity of the on-chip memory, the first 2k data of a row of the two-dimensional array after row transformation is written into the on-chip row transposition memory, the remaining data is written into the off-chip SDRAM, and k is acquired through calculation according to the row transposition result and the capacity of the on-chip row transposition memory. The on-chip memory is divided into two memories A and B used for storing the row transposition partial result and temporarily storing data read from off-chip SDRAM. When data is read from the memory A or B column by column for FFT column transposition, SDRAM is accessed in a row burst manner and data is written into the empty memory A or B alternately, and finally SDRAM is empty through repetitive ping-pong switching between the memories A and B. The row transposed architecture is capable of substantially reducing cross-line accessing frequency of SDRAM and improving two-dimensional FFT execution speed.