Method and interface for interfacing a radio frequency transceiver with a baseband processor
    2.
    发明授权
    Method and interface for interfacing a radio frequency transceiver with a baseband processor 失效
    用于将射频收发器与基带处理器连接的方法和接口

    公开(公告)号:US08588221B2

    公开(公告)日:2013-11-19

    申请号:US13269064

    申请日:2011-10-07

    IPC分类号: H04Q11/00

    摘要: An interface includes three sub-interfaces. A first and second sub-interface receive first/second inbound IQ data streams, respectively, packetize the first/second inbound IQ data streams to obtain first/second inbound IQ data packets, respectively, and transmit the first/second inbound IQ data packets to the baseband processor via a first/second set of RX lanes, respectively. Each first/second inbound IQ data packet comprises a data packet identifier out of a common set of possible data packet identifiers. A third sub-interface receives outbound IQ data packets from the baseband processor via a TX lane, and depacketizes the outbound IQ data packets to obtain an outbound IQ data stream. The third sub-interface receives an RX not-acknowledge signal via the TX lane that identifies a defective first or second inbound IQ data packet within the first/second inbound IQ data packets.

    摘要翻译: 一个接口包括三个子接口。 第一和第二子接口分别接收第一/第二入站IQ数据流,分别对第一/第二入站IQ数据流进行分组以分别获得第一/第二入站IQ数据分组,并将第一/第二入站IQ数据分组发送到 基带处理器分别经由第一/第二组RX通道。 每个第一/第二入站IQ数据分组包括可能数据分组标识符的公共集合中的数据分组标识符。 第三子接口通过TX通道接收来自基带处理器的出站IQ数据分组,并且对出站的IQ数据分组进行解包以获得出站的IQ数据流。 第三子接口经由识别第一/第二入站IQ数据分组内的有缺陷的第一或第二入站IQ数据分组的TX通道接收RX不确认信号。

    METHOD AND INTERFACE FOR INTERFACING A RADIO FREQUENCY TRANSCEIVER WITH A BASEBAND PROCESSOR
    3.
    发明申请
    METHOD AND INTERFACE FOR INTERFACING A RADIO FREQUENCY TRANSCEIVER WITH A BASEBAND PROCESSOR 失效
    无线电频率收发器与基带处理器接口的方法和接口

    公开(公告)号:US20130089012A1

    公开(公告)日:2013-04-11

    申请号:US13269064

    申请日:2011-10-07

    IPC分类号: H04B7/00

    摘要: An interface includes three sub-interfaces. A first and second sub-interface receive first/second inbound IQ data streams, respectively, packetize the first/second inbound IQ data streams to obtain first/second inbound IQ data packets, respectively, and transmit the first/second inbound IQ data packets to the baseband processor via a first/second set of RX lanes, respectively. Each first/second inbound IQ data packet comprises a data packet identifier out of a common set of possible data packet identifiers. A third sub-interface receives outbound IQ data packets from the baseband processor via a TX lane, and depacketizes the outbound IQ data packets to obtain an outbound IQ data stream. The third sub-interface receives an RX not-acknowledge signal via the TX lane that identifies a defective first or second inbound IQ data packet within the first/second inbound IQ data packets.

    摘要翻译: 一个接口包括三个子接口。 第一和第二子接口分别接收第一/第二入站IQ数据流,分别对第一/第二入站IQ数据流进行分组以分别获得第一/第二入站IQ数据分组,并将第一/第二入站IQ数据分组发送到 基带处理器分别经由第一/第二组RX通道。 每个第一/第二入站IQ数据分组包括可能数据分组标识符的公共集合中的数据分组标识符。 第三子接口通过TX通道接收来自基带处理器的出站IQ数据分组,并且对出站的IQ数据分组进行解包以获得出站的IQ数据流。 第三子接口经由识别第一/第二入站IQ数据分组内的有缺陷的第一或第二入站IQ数据分组的TX通道接收RX不确认信号。