公开(公告)号：US06396750B2

公开(公告)日：2002-05-28

申请号：US09888022

申请日：2001-06-22

申请人： Heinz Hönigschmid ,  Georg Braun ,  Andrej Majdic

发明人： Heinz Hönigschmid ,  Georg Braun ,  Andrej Majdic

IPC分类号： G11C700

CPC分类号： G11C29/78 ,  G11C29/702

摘要： An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.

公开(公告)号：US6091625A

公开(公告)日：2000-07-18

申请号：US408479

申请日：1999-09-28

申请人： Georg Braun ,  Carlos Mazure-Espejo ,  Heinz Honigschmid ,  Andrej Majdic

发明人： Georg Braun ,  Carlos Mazure-Espejo ,  Heinz Honigschmid ,  Andrej Majdic

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit. The switching state of the switching unit is changed at least once during a write access operation, so that the information to be written is written to the relevant memory cell by the first sense amplifier initially in noninverted form and then in inverted form. A method for preventing aging in a memory cell in an integrated memory is also provided.

摘要翻译： 集成存储器包括具有位线，字线和可写存储单元的单元阵列。 第一差分读出放大器具有连接到数据线对的连接，第一读出放大器在读访问操作期间从存储器单元之一读取信息，以便随后对其进行放大，并且第一读出放大器将信息写入一个 的存储单元。 相关信息通过数据线对传送为差分信号，并且在每次写入操作期间由第一读出放大器临时存储。 存储器还具有开关单元，通过该开关单元，数据线对连接到第一读出放大器的连接，用于相对于第一读出放大器的连接交换数据线对的线，这取决于开关状态 开关单元。 切换单元的切换状态在写访问操作期间至少改变一次，使得要被写入的信息由第一读出放大器最初以非反相的形式被写入相关存储器单元，然后以倒置形式写入相关的存储单元。 还提供了一种用于防止集成存储器中的存储单元中的老化的方法。