公开(公告)号：US20180004591A1

公开(公告)日：2018-01-04

申请号：US15540232

申请日：2015-01-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Robert J. VOLENTINE ,  Frank L. WU

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/079 ,  G06F11/1417

Abstract: In one example in accordance with the present disclosure, a system for handling memory errors includes a memory module having volatile components and non-volatile components. The system includes a BIOS chip having BIOS code and a BIOS non-volatile (NV) memory. The BIOS NV memory stores error data associated with the memory module that was stored prior to a power-on or reset of the system. The system includes a processor to execute the BIOS code to, after the power-on or reset of the system end before an operating system is loaded; (1) read, from the BIOS NV memory, the error data; and (2) determine, based on the error data, whether to take a corrective action with respect to the memory module.