公开(公告)号：US20220407810A1

公开(公告)日：2022-12-22

申请号：US17354584

申请日：2021-06-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Diego Dompe ,  Laura Salazar ,  Jose Luis Uribe

IPC: H04L12/851 ,  H04L12/803

Abstract: One aspect provides a network switch. The network switch includes hardware-based packet-processing logic for processing received packets, a processing unit, and an offload engine coupled to the processing unit. The offload engine is to offload, from the processing unit, packet-processing operations associated with a subset of the received packets. The offload engine comprises a processor core, at least one hardware packet-processing accelerator for performing the packet-processing operations, and a function-helper logic for interfacing between the processor core and the hardware packet-processing accelerator.

公开(公告)号：US11765092B2

公开(公告)日：2023-09-19

申请号：US17354584

申请日：2021-06-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Diego Dompe ,  Laura Salazar ,  Jose Luis Uribe

IPC: H04L47/2483 ,  H04L47/125 ,  H04L47/2441

CPC classification number: H04L47/2483 ,  H04L47/125 ,  H04L47/2441

Abstract: One aspect provides a network switch. The network switch includes hardware-based packet-processing logic for processing received packets, a processing unit, and an offload engine coupled to the processing unit. The offload engine is to offload, from the processing unit, packet-processing operations associated with a subset of the received packets. The offload engine comprises a processor core, at least one hardware packet-processing accelerator for performing the packet-processing operations, and a function-helper logic for interfacing between the processor core and the hardware packet-processing accelerator.