公开(公告)号：US06230115B1

公开(公告)日：2001-05-08

申请号：US09210820

申请日：1998-12-15

申请人： Hidefumi Ohsaki ,  Yoshiki Nakamura ,  Yoshifumi Sasaki ,  Tomoo Ishida ,  Yasunori Shibayama

发明人： Hidefumi Ohsaki ,  Yoshiki Nakamura ,  Yoshifumi Sasaki ,  Tomoo Ishida ,  Yasunori Shibayama

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A simulator includes a timing simulation section executing timing simulation for a logic circuit of an electronic component, a time management section extracting logical operation time at an output terminal of the electronic component from a result of the simulation, a transmission line simulation section executing simulation of a transmission line connected to the output terminal from the logical operation time extracted by the time management section, and a simulation result processing section combining the result of the simulation by the timing simulation section and a result of the transmission line simulation by the transmission line simulation section.

摘要翻译： 模拟器包括执行电子部件的逻辑电路的定时仿真的定时仿真部，从模拟结果提取电子部件的输出端的逻辑运算时间的时间管理部，执行模拟的 从由时间管理部分提取的逻辑运算时间连接到输出端子的传输线，以及将定时仿真部分的仿真结果与传输线仿真的传输线仿真结果相结合的仿真结果处理部分 部分。