公开(公告)号：US07088418B1

公开(公告)日：2006-08-08

申请号：US09636783

申请日：2000-08-11

申请人： Hidefumi Yamashita ,  Michikazu Noguchi ,  Taroh Hasumi ,  Tatsushi Koike

发明人： Hidefumi Yamashita ,  Michikazu Noguchi ,  Taroh Hasumi ,  Tatsushi Koike

IPC分类号： G02F1/1339 ,  H04B7/14

CPC分类号： G02F1/13394

摘要： The present invention provides a liquid crystal display device having a narrow frame, which is capable of effectively removing a defective display owing to entering of a seal member to a display area. More specifically, the present invention is directed to a liquid crystal display device comprising first and second substrates 1 and 2 disposed at a predetermined gap d1; a liquid crystal sealed in the gap d1; a seal member 4 provided at the gap d1 between the first and second substrates 1 and 2 and outside a display area 3, the seal member 4 being for sealing the liquid crystal; and a wall-like structure 5 provided outside the display area 3 and inside the seal member 4, the wall-like structure 5 being made of a material different from that of the seal member 4 and composed of a plurality of rows.

摘要翻译： 本发明提供一种具有窄框架的液晶显示装置，其能够有效地消除由于密封构件进入显示区域而导致的不良显示。 更具体地，本发明涉及一种液晶显示装置，包括以预定间隙d1设置的第一和第二基板1和2; 密封在间隙d 1中的液晶; 设置在第一和第二基板1和2之间的间隙d 1处和显示区域3外部的密封构件4，密封构件4用于密封液晶; 以及设置在显示区域3的外侧和密封部件4的内部的壁状结构体5，壁状结构体5由与密封部件4不同的材料构成，并且由多列构成。

公开(公告)号：US20080137017A1

公开(公告)日：2008-06-12

申请号：US11972958

申请日：2008-01-11

申请人： Toshiaki Arai ,  Taroh Hasumi

发明人： Toshiaki Arai ,  Taroh Hasumi

IPC分类号： G02F1/1343

CPC分类号： G02F1/134363 ,  G02F2001/133357

摘要： An array substrate, a gate insulating layer, and a data line are deposited sequentially on a liquid crystal cell. At a part of this configuration, a planarizing layer covers the gate insulating layer and the data line. The planarizing layer has a groove formed right above the data line. A common electrode is formed on internal walls of the groove and on the flat surface of the planarizing layer corresponding to the shoulders of the groove. A pixel electrode is formed on the flat surface with a certain distance from the common electrode.

摘要翻译： 阵列基板，栅极绝缘层和数据线依次沉积在液晶单元上。 在该配置的一部分，平坦化层覆盖栅极绝缘层和数据线。 平坦化层具有形成在数据线正上方的凹槽。 公共电极形成在凹槽的内壁上，平坦化层的与凹槽的肩部对应的平坦表面上。 在与公共电极有一定距离的平坦表面上形成像素电极。

公开(公告)号：US07339644B2

公开(公告)日：2008-03-04

申请号：US10732489

申请日：2003-12-11

申请人： Toshiaki Arai ,  Taroh Hasumi

发明人： Toshiaki Arai ,  Taroh Hasumi

IPC分类号： G02F1/1343 ,  G02F1/1333

CPC分类号： G02F1/134363 ,  G02F2001/133357

摘要： An array substrate, a gate insulating layer, and a data line are deposited sequentially on a liquid crystal cell. At a part of this configuration, a planarizing layer covers the gate insulating layer and the data line. The planarizing layer has a groove formed right above the data line. A common electrode is formed on internal walls of the groove and on the flat surface of the planarizing layer corresponding to the shoulders of the groove. A pixel electrode is formed on the flat surface with a certain distance from the common electrode.

摘要翻译： 阵列基板，栅极绝缘层和数据线依次沉积在液晶单元上。 在该配置的一部分，平坦化层覆盖栅极绝缘层和数据线。 平坦化层具有形成在数据线正上方的凹槽。 公共电极形成在凹槽的内壁上，平坦化层的与凹槽的肩部对应的平坦表面上。 在与公共电极有一定距离的平坦表面上形成像素电极。

公开(公告)号：US07570330B2

公开(公告)日：2009-08-04

申请号：US11972958

申请日：2008-01-11

申请人： Toshiaki Arai ,  Taroh Hasumi

发明人： Toshiaki Arai ,  Taroh Hasumi

IPC分类号： G02F1/1333 ,  G02F1/1337

CPC分类号： G02F1/134363 ,  G02F2001/133357

摘要： An array substrate, a gate insulating layer, and a data line are deposited sequentially on a liquid crystal cell. At a part of this configuration, a planarizing layer covers the gate insulating layer and the data line. The planarizing layer has a groove formed right above the data line. A common electrode is formed on internal walls of the groove and on the flat surface of the planarizing layer corresponding to the shoulders of the groove. A pixel electrode is formed on the flat surface with a certain distance from the common electrode.

摘要翻译： 阵列基板，栅极绝缘层和数据线依次沉积在液晶单元上。 在该配置的一部分，平坦化层覆盖栅极绝缘层和数据线。 平坦化层具有形成在数据线正上方的凹槽。 公共电极形成在凹槽的内壁上，平坦化层的与凹槽的肩部对应的平坦表面上。 在与公共电极有一定距离的平坦表面上形成像素电极。

公开(公告)号：US06653178B2

公开(公告)日：2003-11-25

申请号：US10061578

申请日：2002-01-31

申请人： Takatoshi Tsujimura ,  Taroh Hasumi ,  Osamu Tokuhiro ,  Mitsuo Morooka

发明人： Takatoshi Tsujimura ,  Taroh Hasumi ,  Osamu Tokuhiro ,  Mitsuo Morooka

IPC分类号： H01L29786

CPC分类号： H01L29/66757 ,  H01L29/78633

摘要： A thin film transistor and method of making the same is disclosed in which a contact hole is formed with a flattened interface between openings in an inorganic material passivation layer and an organic material interlayer insulating film thereabove. The method includes etching an opening in the interlayer insulating film, using that opening as a mask for subsequently etching a self-aligned opening in the passivation layer, and again etching the interlayer insulating film in a develop back process to obtain a contact hole having a flattened inner sidewall.