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    Memory controller, semiconductor memory device and control method thereof
    1.
    发明授权
    Memory controller, semiconductor memory device and control method thereof 有权
    存储器控制器，半导体存储器件及其控制方法

    公开(公告)号：US09229851B2

    公开(公告)日：2016-01-05

    申请号：US12551898

    申请日：2009-09-01

    申请人： Hiroshi Sukegawa ,  Hidetaka Tsuji ,  Shuji Takano

    发明人： Hiroshi Sukegawa ,  Hidetaka Tsuji ,  Shuji Takano

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G11C16/34

    CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G11C16/349

    摘要： A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

    摘要翻译： 存储器控制器包括逻辑物理地址转换表，访问号码存储部，被配置为存储与逻辑地址相关联地从存储器单元读出数据的访问次数;存储状态检查部，被配置为检查存储状态 如果数据的存储状态处于预定的降级状态，则刷新处理部被配置为执行刷新处理以恢复存储在存储单元中的数据。

    MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF
    2.
    发明申请
    MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 有权
    存储器控制器，半导体存储器件及其控制方法

    公开(公告)号：US20100217919A1

    公开(公告)日：2010-08-26

    申请号：US12551898

    申请日：2009-09-01

    申请人： Hiroshi Sukegawa ,  Hidetaka Tsuji ,  Shuji Takano

    发明人： Hiroshi Sukegawa ,  Hidetaka Tsuji ,  Shuji Takano

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G11C16/349

    摘要： A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

    摘要翻译： 存储器控制器包括逻辑物理地址转换表，访问号码存储部，被配置为存储与逻辑地址相关联地从存储器单元读出数据的访问次数;存储状态检查部，被配置为检查存储状态 如果数据的存储状态处于预定的降级状态，则刷新处理部被配置为执行刷新处理以恢复存储在存储单元中的数据。