公开(公告)号：US07361967B2

公开(公告)日：2008-04-22

申请号：US11050708

申请日：2005-02-07

申请人： Hiroyuki Takahashi ,  Masayuki Yanagisawa ,  Masatoshi Sonoda ,  Yoshinori Ueno

发明人： Hiroyuki Takahashi ,  Masayuki Yanagisawa ,  Masatoshi Sonoda ,  Yoshinori Ueno

IPC分类号： H01L29/00

CPC分类号： H01L23/5258 ,  H01L21/268 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device wherein return wires corresponding to a plurality of fuse wires are arranged collectively in the same region. Moreover, the return wires are arranged in multiple layers. This arrangement creates a region where no return wire is disposed between the fuse wires, thereby permitting an arrangement of the fuse wires at the minimum wiring pitch. Alternatively, the semiconductor device may include fuse strings arranged in a plurality of stages and a plurality of connection wires for supplying signals to the fuse strings in the plurality of stages, respectively, wherein connection wires for other fuse strings are arranged in a region between adjacent fuse strings.

摘要翻译： 一种半导体器件，其中对应于多个熔丝的返回线集中地布置在相同的区域中。 此外，返回线布置成多层。 这种布置形成了在熔丝之间不设置返回布线的区域，从而允许以最小布线间距布置熔丝。 或者，半导体器件可以包括分别布置在多个级中的熔丝串和用于分别向多个级中的熔丝串提供信号的多个连接线，其中用于其它熔丝串的连接线布置在相邻的 保险丝串。

公开(公告)号：US20050181680A1

公开(公告)日：2005-08-18

申请号：US11050708

申请日：2005-02-07

申请人： Hiroyuki Takahashi ,  Masayuki Yanagisawa ,  Masatoshi Sonoda ,  Yoshinori Ueno

发明人： Hiroyuki Takahashi ,  Masayuki Yanagisawa ,  Masatoshi Sonoda ,  Yoshinori Ueno

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01R12/00

CPC分类号： H01L23/5258 ,  H01L21/268 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device wherein return wires corresponding to a plurality of fuse wires are arranged collectively in the same region. Moreover, the return wires are arranged in multiple layers. This arrangement creates a region where no return wire is disposed between the fuse wires, thereby permitting an arrangement of the fuse wires at the minimum wiring pitch. Alternatively, the semiconductor device may include fuse strings arranged in a plurality of stages and a plurality of connection wires for supplying signals to the fuse strings in the plurality of stages, respectively, wherein connection wires for other fuse strings are arranged in a region between adjacent fuse strings.

摘要翻译： 一种半导体器件，其中对应于多个熔丝的返回线集中地布置在相同的区域中。 此外，返回线布置成多层。 这种布置形成了在熔丝之间不设置返回布线的区域，从而允许以最小布线间距布置熔丝。 或者，半导体器件可以包括分别布置在多个级中的熔丝串和用于分别向多个级中的熔丝串提供信号的多个连接线，其中用于其它熔丝串的连接线布置在相邻 保险丝串。

公开(公告)号：US6021075A

公开(公告)日：2000-02-01

申请号：US161217

申请日：1998-09-28

申请人： Yoshinori Ueno

发明人： Yoshinori Ueno

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/78

摘要： A semiconductor memory circuit comprises a plurality of shift redundancy circuits each of which is connected to two of write/read circuits and a redundancy write/read circuit. Also, a plurality of fuse elements are connected to each other in series. One of the fuse elements is connected between one of the shift redundancy circuits and a power supply potential and the others are each connected between two of the shift redundancy circuits. A program circuit is connected to one of the fuse elements disposed at an end portion opposite to the fuse element connected to the power supply potential, and selectively outputs a power supply potential or a ground potential. A plurality of cut fuse detecting circuits are provided which individually detect whether the fuse elements are cut or not, and control each of the write/read circuits and the redundancy write/read circuit in an activated or a inactivated state.

摘要翻译： 半导体存储器电路包括多个移位冗余电路，每个移位冗余电路连接到两个写/读电路和冗余写/读电路。 此外，多个熔丝元件彼此串联连接。 其中一个保险丝元件连接在一个换档冗余电路和一个电源电位之间，另外一个连接在两个移位冗余电路之间。 编程电路连接到设置在与连接到电源电位的熔丝元件相对的端部处的熔丝元件中的一个，并选择性地输出电源电位或接地电位。 提供了多个切断熔丝检测电路，其分别检测熔丝元件是否被切断，并且将控制写入/读取电路和冗余写/读电路中的每一个处于激活状态或非激活状态。

公开(公告)号：US06501108B1

公开(公告)日：2002-12-31

申请号：US09616538

申请日：2000-07-14

申请人： Kenji Suzuki ,  Yoshinori Ueno

发明人： Kenji Suzuki ,  Yoshinori Ueno

IPC分类号： H01L2710

CPC分类号： H01L27/092

摘要： A semiconductor element wherein only one of two mutually adjacent electrodes has a split pattern that is formed on the same layer as the other electrode. The split electrode is connected to a wiring layer provided on a separate layer. When the semiconductor element is a MOSFET, the mutually adjacent electrodes are provided on a source diffusion layer and a drain diffusion layer. Specifically, they serve as a source electrode and a drain electrode, respectively. The split electrode is connected to the source diffusion layer or drain diffusion layer through a single contact hole. This allows the parasitic capacitance in the semiconductor element region to be easily reduced even when the semiconductor element, such as a MOSFET, which comprises the semiconductor integrated circuit is miniaturized.

摘要翻译： 一种半导体元件，其中两个相互相邻的电极中仅一个具有形成在与另一个电极相同的层上的分割图案。 分离电极连接到设置在单独层上的布线层。 当半导体元件是MOSFET时，相互相邻的电极设置在源极扩散层和漏极扩散层上。 具体地说，它们分别用作源电极和漏电极。 分裂电极通过单个接触孔连接到源极扩散层或漏极扩散层。 这使得即使当包括半导体集成电路的诸如MOSFET的半导体元件小型化时，也可以容易地减小半导体元件区域中的寄生电容。

公开(公告)号：US5850364A

公开(公告)日：1998-12-15

申请号：US957582

申请日：1997-10-24

申请人： Yoshinori Ueno

发明人： Yoshinori Ueno

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C7/12

摘要： In a static semiconductor memory device including a plurality of word lines, a plurality of bit line pairs, at lest one precharging line, a plurality of static memory cells connected to one of the word lines and one of the bit line pairs, and a plurality of precharging circuits, connected to the precharging line and one of the bit line pairs, thus charging the one of the bit line pairs, each of the precharging circuits has a similar configuration to one of the static memory cells.

摘要翻译： 在包括多个字线的静态半导体存储器件中，多个位线对，至少一个预充电线，多个静态存储器单元，连接到一条字线和一个位线对，以及多个位线对 的预充电电路，连接到预充电线路和位线对中的一个，从而对位线对中的一个进行充电，每个预充电电路具有与静态存储单元之一相似的配置。