公开(公告)号：US07055135B2

公开(公告)日：2006-05-30

申请号：US10139568

申请日：2002-05-06

申请人： Hong S. Kim ,  Amit Majumdar ,  Sridhar Narayanan

发明人： Hong S. Kim ,  Amit Majumdar ,  Sridhar Narayanan

IPC分类号： G06F9/44

CPC分类号： G06F11/26

摘要： Embodiments of the present invention provide a method and apparatus for debugging an integrated circuit. In particular, one embodiment of the present invention includes steps of: (a) retrieving data from a design data base, and creating a design pattern in a pattern format, which design pattern includes stimulus data for stimuli to be applied to the integrated circuit and design response data for expected responses to the stimuli; (b) generating, responsive to the design pattern, a tester pattern and a test program for input to a tester; (c) testing the integrated circuit in the tester, responsive to the tester pattern and the test program, and generating a datalog that comprises test response data; and (d) generating a file, responsive to the datalog, wherein the test response data are reformatted into the pattern format.