公开(公告)号：US20240348238A1

公开(公告)日：2024-10-17

申请号：US18751562

申请日：2024-06-24

Applicant: Hoseo University Academic Cooperation Foundation

Inventor： Byung-Seong BAE ,  Eui-Joong YUN ,  Je-Hun YOE ,  Seo-Jin KANG ,  Hyuck-Su LEE ,  Jae-Geun WOO

IPC: H03K3/356

CPC classification number: H03K3/356113

Abstract: A CMOS inverter circuit includes a first and second PMOS transistor connected in series to a power supply voltage (VDD) and a first NMOS transistor connected in series with the second PMOS transistor and to ground (GND). All transistors receive the same input signal.
This configuration enables normal logic gate operation even when the P-channel characteristics of the PMOS transistors are shifted. The channel widths of the first and second PMOS transistors can be varied to adjust circuit performance.

公开(公告)号：US20250124844A1

公开(公告)日：2025-04-17

申请号：US18628919

申请日：2024-04-08

Applicant: Hoseo University Academic Cooperation Foundation

Inventor： Byung-Seong BAE ,  Hyuck-Su LEE ,  Seo-Jin KANG

IPC: G09G3/20

Abstract: The present invention relates to a scan drive circuit and, more specifically, to a scan drive circuit that is insensitive to changes in the characteristics of transistors, enabling stable operation even when such changes occur within a certain range. Accordingly, the scan drive circuit provides the advantage of high yield when applied not only to conventional rigid substrates but also to flexible or stretchable substrates.
According to the present invention, a scan drive circuit is provided that operates normally regardless of whether the transistor exhibits enhancement-type or depletion-type characteristics, thereby eliminating the need to modify the circuit or employ complex designs based on the characteristics of the transistors.