公开(公告)号：US20130234252A1

公开(公告)日：2013-09-12

申请号：US13412714

申请日：2012-03-06

申请人： Hsiang-Chen LEE ,  Ping-Chia Shih ,  Ke-Chi Chen ,  Chih-Ming Wang ,  Chi-Cheng Huang

发明人： Hsiang-Chen LEE ,  Ping-Chia Shih ,  Ke-Chi Chen ,  Chih-Ming Wang ,  Chi-Cheng Huang

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857

摘要： An integrated circuit includes a substrate, a first semiconductor device, a second semiconductor device and an interlayer dielectric layer. At least one isolation structure has been formed in the he substrate so as to separate the substrate into a first active region and a second active region. The first semiconductor device disposed on the first active region of the substrate includes a first gate insulating layer and a poly-silicon gate stacked on the substrate sequentially. The second semiconductor device disposed on the second active region of the substrate includes a second gate insulating layer and a metal gate stacked on the substrate sequentially. The material of the second gate insulating layer is different from that of the first gate insulating layer. The thickness of the metal gate is greater than that of the poly-silicon gate. The interlayer dielectric layer is disposed on the substrate and covering the first semiconductor device.

摘要翻译： 集成电路包括衬底，第一半导体器件，第二半导体器件和层间电介质层。 在衬底中形成至少一个隔离结构，以将衬底分离成第一有源区和第二有源区。 设置在基板的第一有源区上的第一半导体器件包括依次层叠在基板上的第一栅极绝缘层和多晶硅栅极。 设置在基板的第二有源区上的第二半导体器件包括依次层叠在基板上的第二栅极绝缘层和金属栅极。 第二栅极绝缘层的材料与第一栅极绝缘层的材料不同。 金属栅极的厚度大于多晶硅栅极的厚度。 层间介质层设置在基板上并覆盖第一半导体器件。