公开(公告)号：US20230236891A1

公开(公告)日：2023-07-27

申请号：US18191134

申请日：2023-03-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Chen XIN ,  Honghui YUAN ,  Chun Hang LEE

IPC: G06F9/50 ,  G06F17/14 ,  G06F7/523 ,  G06F7/78

CPC classification number: G06F9/5027 ,  G06F17/144 ,  G06F7/523 ,  G06F7/78

Abstract: A neural network accelerator is provided, including: a preprocessing module (301), configured to perform first forward winograd transform on a target matrix corresponding to an input feature map, to obtain a transformed target matrix, where the preprocessing module (301) is further configured to perform second forward winograd transform on a convolution kernel, to obtain a transformed convolution kernel; a matrix operation module (302), configured to perform a matrix multiplication operation on a first matrix and a second matrix, to obtain a multiplication result, where the first matrix is constructed based on the transformed target matrix, and the second matrix is constructed based on the transformed convolution kernel; and a vector operation module (303), configured to perform inverse winograd transform on the multiplication result, to obtain an output feature map.

公开(公告)号：US20200344000A1

公开(公告)日：2020-10-29

申请号：US16926094

申请日：2020-07-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yaron BEN-ARIE ,  Chun Hang LEE ,  Genadiy TSODIK ,  Shimon SHILO ,  Doron EZRI

IPC: H04L1/00 ,  H04B7/0413

Abstract: The invention relates to an apparatus for selecting candidates in a K-Best algorithm of a MIMO decoder. The K-Best algorithm uses a layered structure comprising a first layer and subsequent layers. In each subsequent layer 2L candidates are selected by iteratively carrying out a selection step, wherein in the selection step the apparatus is configured to calculate and select at least two candidates having minimum distance values of a candidate group, and after each iteratively carried out selection step, the selected at least two candidates are sent to a further subsequent layer for iteratively generating a further candidate group of 2L candidates in the further subsequent layer.

公开(公告)号：US20220206757A1

公开(公告)日：2022-06-30

申请号：US17698068

申请日：2022-03-18

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Chun Hang LEE ,  Zhenjiang DONG

IPC: G06F7/544

Abstract: A multiplier (500) configured to simultaneously implement a plurality of low bit width multiplication operations is provided. The multiplier (500) includes a multiplicator input end (550) for receiving two low bit width multiplicators, a multiplicand input end (560) for receiving two low bit width multiplicands, a mask circuit (540) for masking each low bit width multiplicator, and a multiplication operation circuit (502) for multiplying a mask result and a multiplicand. When a sum of bit widths of the multiplicators is smaller than the multiplicator input end (550) and a sum of bit widths of the multiplicands is smaller than the multiplicand input end (560), masking is performed on each of the low bit width multiplicators, so that the multiplier (500) may respectively implement two low bit width multiplication operations, which resolves a waste of hardware resources that occurs because the multiplier can only process multiplication operations in one data format.