公开(公告)号：US20230022190A1

公开(公告)日：2023-01-26

申请号：US17944031

申请日：2022-09-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Elnaz Ebrahimi ,  Ehsan Khish Ardestani Zadeh ,  Wei-Yu Chen ,  Liang Peng

IPC: G06F12/0862 ,  G06F12/0811

Abstract: An apparatus includes a processor core and a memory hierarchy. The memory hierarchy includes main memory and one or more caches between the main memory and the processor core. A plurality of hardware pre-fetchers are coupled to the memory hierarchy and a pre-fetch control circuit is coupled to the plurality of hardware pre-fetchers. The pre-fetch control circuit is configured to compare changes in one or more cache performance metrics over two or more sampling intervals and control operation of the plurality of hardware pre-fetchers in response to a change in one or more performance metrics between at least a first sampling interval and a second sampling interval.

公开(公告)号：US12282429B2

公开(公告)日：2025-04-22

申请号：US17944031

申请日：2022-09-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Elnaz Ebrahimi ,  Ehsan Khish Ardestani Zadeh ,  Wei-Yu Chen ,  Liang Peng

IPC: G06F12/0862 ,  G06F12/0811

Abstract: An apparatus includes a processor core and a memory hierarchy. The memory hierarchy includes main memory and one or more caches between the main memory and the processor core. A plurality of hardware pre-fetchers are coupled to the memory hierarchy and a pre-fetch control circuit is coupled to the plurality of hardware pre-fetchers. The pre-fetch control circuit is configured to compare changes in one or more cache performance metrics over two or more sampling intervals and control operation of the plurality of hardware pre-fetchers in response to a change in one or more performance metrics between at least a first sampling interval and a second sampling interval.