公开(公告)号：US20190026225A1

公开(公告)日：2019-01-24

申请号：US16138824

申请日：2018-09-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiongli GU ,  Lei FANG ,  Peng LIU ,  Qi HU

IPC: G06F12/0817

Abstract: A multiple chip multiprocessor cache coherence operation method and a multiple chip multiprocessor are disclosed. The method includes: receiving a write request for a first data block; finding, in an on-chip directory of the first processor chip, an on-chip directory entry corresponding to the first data block based on an identifier of the first data block, determining, from the found on-chip directory entry, a core identifier of a processor core storing the first data block, sending, to the processor core corresponding to the core identifier, an instruction message for deleting the first data block, skipping sending an inter-chip directory query request for the first data block, and instructing the first processor core to write the to-be-written data into a private cache of the first processor core.