公开(公告)号：US10185085B2

公开(公告)日：2019-01-22

申请号：US15839422

申请日：2017-12-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yourui Huangfu ,  Shaoqing Liu ,  Yingchun Yang ,  Chen Qiu

IPC: G02B6/122 ,  G02B6/26 ,  G02B6/35 ,  G02B6/43 ,  H04B10/80 ,  H04Q11/00

Abstract: An on-chip optical interconnection structure and network, where the on-chip optical interconnection structure includes M levels of optical switches, and mth-level optical switches in the M levels of optical switching devices include 2m-1 optical switches. Each optical switch in (i-1)th-level optical switches in the M levels of optical switches is coupled to two optical switches in ith-level optical switches. Two optical switches in the ith-level optical switches coupled to a same optical switch in the (i-1)th-level optical switches are coupled. The on-chip optical interconnection network is divided into levels, and switches coupled in a grid manner are formed such that hierarchical switching may be performed, and conflicts and delays in communication are reduced.

公开(公告)号：US20180100965A1

公开(公告)日：2018-04-12

申请号：US15839422

申请日：2017-12-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yourui Huangfu ,  Shaoqing Liu ,  Yingchun Yang ,  Chen Qiu

IPC: G02B6/122 ,  G02B6/35 ,  G02B6/43 ,  H04B10/80 ,  H04Q11/00

CPC classification number: G02B6/122 ,  G02B6/26 ,  G02B6/3546 ,  G02B6/43 ,  H04B10/803 ,  H04Q11/0005

Abstract: An on-chip optical interconnection structure and network, where the on-chip optical interconnection structure includes M levels of optical switches, and mth-level optical switches in the M levels of optical switching devices include 2m-1 optical switches. Each optical switch in (i-1)th-level optical switches in the M levels of optical switches is coupled to two optical switches in ith-level optical switches. Two optical switches in the ith-level optical switches coupled to a same optical switch in the (i-1)th-level optical switches are coupled. The on-chip optical interconnection network is divided into levels, and switches coupled in a grid manner are formed such that hierarchical switching may be performed, and conflicts and delays in communication are reduced.