公开(公告)号：US11004502B2

公开(公告)日：2021-05-11

申请号：US16807594

申请日：2020-03-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sijie Chi ,  Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: A storage unit and a static random access memory (SRAM), where storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first metal-oxide-semiconductor (MOS) transistor. A gate of the first MOS transistor is coupled to the first storage bit, a source of the first MOS transistor is coupled to a first read line, and a drain of the first MOS transistor is coupled to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line, or in a second state, the second read line is a read word line, and the first read line is a read bit line. The storage unit according to embodiments of the present invention can implement an exchange between a read word line and a read bit line.

公开(公告)号：US11475943B2

公开(公告)日：2022-10-18

申请号：US17226614

申请日：2021-04-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sijie Chi ,  Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.

公开(公告)号：US20210295906A1

公开(公告)日：2021-09-23

申请号：US17226614

申请日：2021-04-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sijie Chi ,  Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou

IPC: G11C11/419 ,  G11C11/54 ,  G06N3/063

Abstract: A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.