公开(公告)号：US20210119586A1

公开(公告)日：2021-04-22

申请号：US17135331

申请日：2020-12-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Taotao Yan ,  Kerou Wang ,  Wei Wu

IPC: H03F1/42 ,  H03F3/45

Abstract: An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.

公开(公告)号：US11894811B2

公开(公告)日：2024-02-06

申请号：US17135331

申请日：2020-12-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Taotao Yan ,  Kerou Wang ,  Wei Wu

IPC: H03F3/45 ,  H03F1/42

CPC classification number: H03F1/42 ,  H03F3/4521 ,  H03F2200/36 ,  H03F2200/451

Abstract: An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.