MATRIX OPERATION METHOD AND ACCELERATOR
    1.
    发明公开

    公开(公告)号:US20230161835A1

    公开(公告)日:2023-05-25

    申请号:US18093929

    申请日:2023-01-06

    CPC classification number: G06F17/16 G06F13/28 G06F2213/28

    Abstract: A matrix operation method is provided, applied to an accelerator configured to perform a matrix operation. A matrix operation accelerator (100) respectively stores, in response to a received matrix operation instruction, subsets of a first matrix and subsets of a second matrix in a first storage space and a second storage space of a memory (120); stores, in a third storage space of the memory (120), subsets obtained after the subsets of the first matrix are multiplied by the subsets of the second matrix; and performs matrix operations on the subsets of the first matrix and the subsets of the second matrix based on the matrix operation instruction, to obtain matrix operation results. The dedicated matrix operation accelerator (100) is used to perform a matrix operation, so that a large-scale matrix operation can be completed in relatively short time, thereby offloading a matrix operation burden of a processor.

    DATA TRANSMISSION METHOD AND RELATED DEVICE

    公开(公告)号:US20220327094A1

    公开(公告)日:2022-10-13

    申请号:US17843825

    申请日:2022-06-17

    Abstract: A data transmission method, performed by a receive end, includes: receiving notification information that is about to-be-transmitted data and that is sent by a transmit end, where the notification information includes a size of the to-be-transmitted data of the transmit end; generating a plurality of RDMA read requests based on the size of the to-be-transmitted data; and sending the plurality of RDMA read requests to the transmit end, where a bandwidth occupied by data read by the plurality of sent RDMA read requests is less than or equal to an ingress bandwidth of the receive end.

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