公开(公告)号：US10749485B2

公开(公告)日：2020-08-18

申请号：US16241674

申请日：2019-01-07

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiwei Hong ,  Xianglin Li ,  Yuxiang Xiao

IPC: H04K1/02 ,  H04L25/49 ,  H03F3/213 ,  H03F1/32 ,  H03F3/195

Abstract: Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.

公开(公告)号：US20190140605A1

公开(公告)日：2019-05-09

申请号：US16241674

申请日：2019-01-07

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiwei Hong ,  Xianglin Li ,  Yuxiang Xiao

IPC: H03F3/213 ,  H03F1/32

Abstract: Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.