公开(公告)号：US20140114640A1

公开(公告)日：2014-04-24

申请号：US14142567

申请日：2013-12-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Handong YE ,  Jiong CAO ,  Xiaochun YE ,  Da WANG

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F11/261

Abstract: The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.

Abstract translation: 本发明提供并行模拟多个处理器的方法和系统，以及调度器。 在本实施例中，调度器在多个处理器的并行仿真期间将需要调试的待仿真处理器的调试接口信息映射到调度器上，使得调度器能够通过使用主线程来调试待调制程序， 模拟处理器需要通过待仿真处理器的调试接口进行调试，需要调试接口信息指示的调试，从而在并行仿真多个处理器期间实现调试。