公开(公告)号：US20220414052A1

公开(公告)日：2022-12-29

申请号：US17897295

申请日：2022-08-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Guozhu Li ,  Xinwei Hu

IPC: G06F15/80 ,  G06F9/445 ,  G06F9/30

Abstract: A multi-core processor includes a primary processor core and a secondary processor core coupled to the primary processor core. The primary processor core has first instruction space, and the secondary processor core has second instruction space. The primary processor core is configured to execute a first code segment in a target program, where the target program further includes a second code segment, the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space, and send an address of the second code segment to the secondary processor core through a configuration interface of the secondary processor core.

公开(公告)号：US12242415B2

公开(公告)日：2025-03-04

申请号：US17897295

申请日：2022-08-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Guozhu Li ,  Xinwei Hu

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/445

Abstract: A multi-core processor includes a primary processor core and a secondary processor core coupled to the primary processor core. The primary processor core has first instruction space, and the secondary processor core has second instruction space. The primary processor core is configured to execute a first code segment in a target program, where the target program further includes a second code segment, the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space, and send an address of the second code segment to the secondary processor core through a configuration interface of the secondary processor core.