公开(公告)号：US20210250299A1

公开(公告)日：2021-08-12

申请号：US17248519

申请日：2021-01-28

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Fangming LIU ,  Hai JIN ,  Miao LI

IPC: H04L12/851 ,  H04L12/803 ,  G06F16/22 ,  H04L12/24

Abstract: The present invention relates to a container-based network function virtualization (NFV) platform, comprising at least one master node and at least one slave node, the master node is configured to, based on interference awareness, assign container-based network functions (NFs) in a master-slave-model-based, distributed computing system that has at least two slave nodes to each said slave node in a manner that relations among characteristics of the to-be-assigned NFs, info of load flows of the to-be-assigned NFs, communication overheads between the individual slave nodes, processing performance inside individual slave nodes, and load statuses inside individual said slave nodes are measured.

公开(公告)号：US20190213029A1

公开(公告)日：2019-07-11

申请号：US16135598

申请日：2018-09-19

Applicant: Huazhong University of Science and Technology

Inventor： Fangming LIU ,  Hai JIN ,  Xiaoyao LI

IPC: G06F9/455 ,  G06F9/50 ,  G06F15/78

Abstract: The present invention relates to an FPGA-based method and system for network function accelerating. The method comprises: building a network function accelerating system that includes a physical machine and an accelerator card connected through a PCIe channel, wherein the physical machine includes a processor and the accelerator card includes an FPGA, in which the accelerator card serves to provide network function accelerating for the processor; the processor being configured to: when it requires the accelerator card to provide network function accelerating, check whether there is any required accelerator module present in the FPGA, and if yes, acquire an accelerating function ID corresponding to the required accelerator module, and if not, select at least one partial reconfigurable region in the FPGA and configure it into the required accelerator module and generate a corresponding accelerating function ID; and/or sending an accelerating request to the FPGA.