公开(公告)号：US08402420B2

公开(公告)日：2013-03-19

申请号：US12926505

申请日：2010-11-23

申请人： Hui-Ru Jiang ,  Hua-Yu Chang ,  Chih-Long Chang

发明人： Hui-Ru Jiang ,  Hua-Yu Chang ,  Chih-Long Chang

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

CPC分类号： G06F17/5077 ,  G06F2217/82

摘要： A method for designing an optimal wiring topology for electromigration avoidance is disclosed. The wiring topology includes multiple sources, multiple sinks and multiple wires. The method includes the following steps: A feasible wire, a wire of the shortest length connecting each pair of source and sink, is calculated, and the capacity of each feasible wire is decided. An initial feasible topology is found. A flow network is created based on the initial topology. Negative cycles are iteratively checked and removed until no more negative cycles.

摘要翻译： 公开了一种用于设计避免电迁移的最佳布线拓扑的方法。 布线拓扑包括多个源，多个汇和多个线。 该方法包括以下步骤：计算可行线，连接每对源和汇的最短长度的导线，并确定每条可行线的容量。 找到一个初步的可行拓扑。 基于初始拓扑创建流网络。 反循环检查和去除负循环，直到不再有负循环。

公开(公告)号：US08776000B2

公开(公告)日：2014-07-08

申请号：US13671398

申请日：2012-11-07

申请人： Hua-Yu Chang ,  Hui-Ru Jiang ,  Yao-Wen Chang

发明人： Hua-Yu Chang ,  Hui-Ru Jiang ,  Yao-Wen Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5068 ,  G06F2217/72 ,  G06F2217/84

摘要： A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, decomposing the timing violating path into at least one violating path segment, determining a smooth curve from each timing violating path and determining a plurality of reference points along the smooth curve, computing a fixability parameter of each gate on the violating path segment, extracting at least one gate according to the fixability parameters, and selecting one spare cell and disposing the selected spare cell on the violating path segment.

摘要翻译： 在电路中实现定时ECO的方法包括以下步骤：对电路执行静态时序分析，以便确定电路的至少一个违规路径，将违规路径分解为至少一个违规路径段，确定 从每个违规路线平滑曲线，沿平滑曲线确定多个参考点，计算违反路径段上每个门的可定位参数，根据定影参数提取至少一个门，并选择一个备用单元并处理 违规路径段上的选定备用单元。

公开(公告)号：US20130298097A1

公开(公告)日：2013-11-07

申请号：US13671398

申请日：2012-11-07

申请人： Hua-Yu Chang ,  Hui-Ru Jiang ,  Yao-Wen Chang

发明人： Hua-Yu Chang ,  Hui-Ru Jiang ,  Yao-Wen Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5068 ,  G06F2217/72 ,  G06F2217/84

摘要： A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, decomposing the timing violating path into at least one violating path segment, determining a smooth curve from each timing violating path and determining a plurality of reference points along the smooth curve, computing a fixability parameter of each gate on the violating path segment, extracting at least one gate according to the fixability parameters, and selecting one spare cell and disposing the selected spare cell on the violating path segment.

摘要翻译： 在电路中实现定时ECO的方法包括以下步骤：对电路执行静态时序分析，以便确定电路的至少一个违规路径，将违规路径分解为至少一个违规路径段，确定 从每个违规路线平滑曲线，沿平滑曲线确定多个参考点，计算违反路径段上每个门的可定位参数，根据定影参数提取至少一个门，并选择一个备用单元并处理 违规路径段上的选定备用单元。

公开(公告)号：US20110310102A1

公开(公告)日：2011-12-22

申请号：US12817294

申请日：2010-06-17

申请人： Hua-Yu Chang

发明人： Hua-Yu Chang

IPC分类号： G06T17/20

CPC分类号： G06T17/20

摘要： Systems and methods for subdividing patches and storing control points are described. At least one embodiment is a method for storing vertex data in a graphics processor. The method comprises receiving a patch to be tessellated, subdividing the patch into a plurality of triangles, and identifying control points of each of the plurality of triangles. The method further comprises assigning an identifier to each of the vertices, and selectively storing only a portion of the vertices in a memory.

摘要翻译： 描述用于分割补丁和存储控制点的系统和方法。 至少一个实施例是用于将顶点数据存储在图形处理器中的方法。 该方法包括接收待镶嵌的贴片，将贴片细分成多个三角形，以及识别多个三角形中的每一个的控制点。 该方法还包括将标识符分配给每个顶点，并且仅选择性地将一部分顶点存储在存储器中。