公开(公告)号：US20230197726A1

公开(公告)日：2023-06-22

申请号：US18064508

申请日：2022-12-12

Applicant: IMEC VZW

Inventor： Book Teik Chan ,  Dunja Radisic ,  Anne Vandooren ,  Juergen Boemmels

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823857 ,  H01L21/823828 ,  H01L29/0673

Abstract: Example embodiments relate to methods for forming a stacked FET device. An example method includes forming a bottom FET device that includes a source, a drain, at least one channel layer between the source and drain, and a bottom gate electrode arranged along the at least one channel layer. The method also includes forming a bonding layer over the bottom FET. Additionally, the method includes forming a top FET device on the bonding layer. Forming the top FET device includes forming a device layer structure. The device layer structure includes at least one channel layer of a channel semiconductor material and a top sacrificial layer of a sacrificial semiconductor material. Further, the method includes replacing the top sacrificial layer with a dummy layer of a dielectric dummy material, forming a gate-to-gate contact trench, depositing gate electrode material, and forming a source and a drain of the top FET device.