公开(公告)号：US20160162290A1

公开(公告)日：2016-06-09

申请号：US14785385

申请日：2013-04-19

Applicant: INSTITUTE OF AUTOMATION, CHINESE ACADEMY OF SCIENCES

Inventor： Donglin Wang ,  Shaolin Xie ,  Yongyong Yang ,  Leizu Yin ,  Lei Wang ,  Zijun Liu ,  Tao Wang ,  Xing Zhang

IPC: G06F9/30

CPC classification number: G06F9/30

Abstract: The present disclosure provides a processor having polymorphic instruction set architecture. The processor comprises a scalar processing unit, at least one polymorphic instruction processing unit, at least one multi-granularity parallel memory and a DMA controller. The polymorphic instruction processing unit comprises at least one functional unit. The polymorphic instruction processing unit is configured to interpret and execute a polymorphic instruction and the functional unit is configured to perform specific data operation tasks. The scalar processing unit is configured to invoke the polymorphic instruction and inquire an execution state of the polymorphic instruction. The DMA controller is configured to transmit configuration information for the polymorphic instruction and transmit data required by the polymorphic instruction to the multi-granularity parallel memory. With the present disclosure, programmers can redefine a processor instruction set based on algorithm characteristics of applications after tape-out of a processor.

Abstract translation: 本公开提供了具有多态指令集架构的处理器。 处理器包括标量处理单元，至少一个多态指令处理单元，至少一个多粒度并行存储器和DMA控制器。 多态指令处理单元包括至少一个功能单元。 多态指令处理单元被配置为解释并执行多态指令，并且功能单元被配置为执行特定的数据操作任务。 标量处理单元被配置为调用多态指令并查询多态指令的执行状态。 DMA控制器被配置为发送多态指令的配置信息并将多态指令所需的数据发送到多粒度并行存储器。 利用本公开，程序员可以在处理器输出之后基于应用的算法特性来重新定义处理器指令集。