Phase locked loop
    1.
    发明授权
    Phase locked loop 失效
    相位锁定环

    公开(公告)号:US3731219A

    公开(公告)日:1973-05-01

    申请号:US3731219D

    申请日:1972-06-13

    CPC classification number: H04J3/073

    Abstract: A hybrid digital phase locked loop is disclosed to recover an isochronous clock from a ''''stuffed'''' multiplexed input signal as found in an asynchronous PCM demultiplexer. A low frequency voltage controlled multivibrator is controlled by the output of a phase comparator. The phase comparator is coupled to the input signal and the output signal of a distributor. The distributor is controlled by the multivibrator to sequentially switch a multiphase output signal of a crystal oscillator to provide the output signal of the distributor. This arrangement overcomes the requirement of a voltage controlled crystal oscillator per channel group in the demultiplexer.

    Abstract translation: 公开了一种混合数字锁相环,用于从异步PCM解复用器中发现的“填充”复用输入信号恢复同步时钟。 低频电压控制的多谐振荡器由相位比较器的输出控制。 相位比较器耦合到输入信号和分配器的输出信号。 分配器由多谐振荡器控制以依次切换晶体振荡器的多相输出信号以提供分配器的输出信号。 这种布置克服了在解复用器中每个通道组的压控晶体振荡器的要求。

    Amplitude stabilized l.c. oscillator with output circuits for producing semi-sinusoidal clock pulses
    2.
    发明授权
    Amplitude stabilized l.c. oscillator with output circuits for producing semi-sinusoidal clock pulses 失效
    AMPLITUDE STABILIZED L.C. 具有输出电路的振荡器,用于生产半双工时钟脉冲

    公开(公告)号:US3761833A

    公开(公告)日:1973-09-25

    申请号:US3761833D

    申请日:1972-08-14

    Inventor: MADER H

    CPC classification number: H03K4/92

    Abstract: This self-oscillating clock driver circuit generates two halfsinusoidal, non-overlapping phases of output intended primarily for driving two-phase MOST circuits in a quick-step push-button dial telephone. A Hartley oscillator, modified to include an amplitude stabilization circuit, drives a pair of transistor output circuits which in turn drive the capacitive loads in a push-pull manner. The clock driver arrangement also functions as a master oscillator in the subscriber handset to provide the push-button tone frequencies.

    Abstract translation: 该自振荡时钟驱动器电路产生两个半正弦,非重叠的输出相,主要用于驱动快速按钮拨号电话中的两相MOST电路。 修改为包括幅度稳定电路的哈特利振荡器驱动一对晶体管输出电路,其依次以推挽方式驱动电容性负载。 时钟驱动器布置还用作用户手机中的主振荡器以提供按钮音频率。

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